Metal oxide semiconductor ("MOS") circuits and complementary metal oxide semiconductor ("CMOS") circuits have operating characteristics which are strongly dependent upon temperature. In particular, the conductance of a MOS or of a CMOS field effect transistor ("FET") decreases with increasing temperature. As a result of this variation, circuit performance must sometimes be reduced to keep a circuit functional over a reasonable temperature range. FET performance is generally reduced so that the transistor will not over-conduct in the low temperature domain. This compromise results in a less capable circuit given a particular level of technology. In most instances, a circuit designed to operate over a wide temperature range simply does not switch as fast as a circuit designed to operate over a narrow temperature range.
Over-conductance in FET circuits causes a momentarily high rate of current change per unit time through the FET when the FET turns on. This change, when coupled with the inherent inductance of a circuit, causes an induced electromotive force ("EMF") which opposes the flow of current. This induced EMF will create noise in the voltage supply and ground plane. This in turn may cause various errors known in the art such as clock cycle failure.
Therefore, a need has arisen for a circuit for MOS and CMOS applications which is able to compensate for temperature induced conductance variation.